1. Technical Field
The present invention relates in general to testing and verification and in particular to creating coverage models for testing schemes. Still more particularly, the present invention relates to a system, method and computer program product for improving efficiency in generating coverage data for a circuit testing scheme.
2. Description of the Related Art
With the increasing penetration of processor-based systems into every facet of human activity, demands have increased on the processor and application-specific integrated circuit (ASIC) development and production community to produce systems that are free from design flaws. Circuit products, including microprocessors, digital signal and other special-purpose processors, and ASICs, have become involved in the performance of a vast array of critical functions, and the involvement of microprocessors in the important tasks of daily life has heightened the expectation of error-free and flaw-free design. Whether the impact of errors in design would be measured in human lives or in mere dollars and cents, consumers of circuit products have lost tolerance for results polluted by design errors. Consumers will not tolerate, by way of example, miscalculations on the floor of the stock exchange, in the medical devices that support human life, or in the computers that control their automobiles. All of these activities represent areas where the need for reliable circuit results has risen to a mission-critical concern.
In response to the increasing need for reliable, error free designs, the processor and ASIC design and development community has developed rigorous, if incredibly expensive, methods for testing and verification. Simulation has been a traditional method for verifying such complex designs as processor chips. Since the simulation time for a design grows, in the worst case, as the cube of the number of logic elements, simulation and verification of complex systems is one of the most time-consuming computing tasks today. It is therefore important to use simulation cycles effectively, with the aim that few bugs escape and development time is reduced. One way to increase the simulation effectiveness is to use a simulation coverage tool that helps measure simulation effectiveness and refine the simulation process.
A coverage model defines the basic characteristics of events that constitute the coverage space. Conversely, a coverage space is a collection of all possible events or simulations that can legally occur in hardware. A coverage tool measures how much of a design has been exercised against a chosen coverage model. The operative word is exercised, because a coverage tool does not measure the correctness of a design. Several coverage models are possible for any given design.
Conventional methods for generating coverage data have serious drawbacks. Foremost among them, conventional coverage models depend on reading the input to a testing scheme (in the form of input traces) to determine what portions of the coverage space have been tested. While the input states are relevant, a model based on input states is not sufficiently descriptive of the internal state of hardware under test.
Second, conventional systems for generating coverage models are incredibly labor-intensive. Conventional systems for generating coverage models depend on the time-intensive creation, usually in a programming language, of detailed scripts for each desired coverage model of a given item of simulated hardware. Because system designs change rapidly and coverage models must likewise change rapidly, the investment of time necessary to develop coverage models has prohibited their most effective possible applications.
What is needed is a more efficient method for developing more accurate coverage models.